`timescale 1ns / 1ps
/************************************************************\
 **  Copyright (c) 2022-2023 Gonsin, Inc.
 **  All Right Reserved.
 **  Author: http://www.anlogic.com/
 **  Description: FDPE
 **  Rev 1.0
\************************************************************/

//***********************//
//带有时钟使能和异步置位的 D 触发器
module FDPE (
input C,
input CE,
input PRE,
input D,
output Q
);

//初始化Q输出值
parameter INIT = 1'b1;

reg q_o;
initial q_o = INIT;
assign Q = q_o;

//真值表
always@(posedge PRE or posedge C) begin
  if(PRE)
    q_o <= 1'b1;
  else if(CE)
    q_o <= D;
end

/*
//路径延迟
specify
  (posedge PRE => (Q +: 1'b1)) = (0, 0);
  if (!PRE && CE)
    (posedge C => (Q +: D)) = (100, 100);
endspecify
*/

endmodule

//***********************//
//D 触发器
module FD (
input C,
input D,
output Q
);

//初始化Q输出值
parameter INIT = 1'b0;

reg q_o;
initial q_o = INIT;
assign Q = q_o;

//真值表
always@(posedge C) 
  q_o <= D;

/*
//路径延迟
specify
  (posedge C => (Q +: D)) = (0, 0);
endspecify
*/
endmodule

